LDMOS minority carrier shunting
US9123804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2014 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Jun 11, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/50
Abstract
A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.