Methods for fabricating FinFET integrated circuits using laser interference lithography techniques

US9123825B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Sven Beyer · Dresden, DE
• Alexander Ebermann · Dresden, DE
• Carsten Grass · Dresden, DE
• Jan Hoentschel · Dresden, DE

Key dates

• Filing date: Jan 13, 2014
• Grant date: Sep 1, 2015
• Expiry date: Jan 13, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions.