Methods for fabricating integrated circuits with fully silicided gate electrode structures

US9123827B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Sven Beyer · Dresden, DE
• Jan Hoentschel · Dresden, DE
• Alexander Ebermann · Dresden, DE
• Carsten Grass · Dresden, DE

Key dates

• Filing date: Jan 13, 2014
• Grant date: Sep 1, 2015
• Expiry date: Jan 16, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31144
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.