Digital clock placement engine apparatus and method with duty cycle correction and quadrature placement
US9124257B2 · kind B2 · utility
4Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2011 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Dec 29, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital clock placement engine has circuitry that adjusts a duty cycle of a clock signal and adjusts the locations of the rising/falling edges of the clock signal for purposes of data sampling or other operations. In a forwarded-clock interface implementation, a clock signal is received along with a data signal, and the received clock signal may be distorted to due various factors. To enable the received data signal to be sampled correctly, the clock placement engine generates a recovered clock signal having rising and falling edges that are placed/timed between the rising and falling edges of the received clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.