Error correction coding in non-volatile memory
US9124300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2013 |
| Grant date | Sep 1, 2015 |
| Priority date | — |
| Expiry date | Aug 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/255
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method includes encoding data bits into codewords according to a first error correction encoding scheme. The method includes storing the codewords into a memory and generating a combined codeword by encoding, at the memory, the codewords according to a second error correction encoding scheme to generate parity bits of the combined codeword. The method includes, after storing the codewords into the memory, storing the parity bits of the combined codeword into the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.