Patent · US Active

Link equalization mechanism

US9124455B1 · kind B1 · utility

4Cited by

0References

25Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Su Wei Lim · Klang, MY
Ronald W. Swartz · Loomis, US
Yueming Jiang · Rancho Cordova, US
Hooi Kar Loo · Bayan Lepas, MY
Athourina Gevergiz · San Jose, US
Bruce A. Tennant · Hillsboro, US
Yick Yaw Ho · Folsom, US
Poh Thiam Teoh · Bandar Baru Sungai Buloh, MY
Jennifer Chin · Bayan Lepas, MY
Hui Shi · Nanchang, CN

Key dates

Filing date	Sep 24, 2014
Grant date	Sep 1, 2015
Priority date	—
Expiry date	Sep 24, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2025/03681
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.