Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages
US9129078B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2013 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Oct 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.