Single port memory that emulates dual port memory
US9129661B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2013 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Feb 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-port memory that operates in single-cycle dual-port mode has a logical capacity of N=k·m memory words and (k+1) single-port RAM having an overall physical capacity of (k+1)·m memory words. A status register holds words identifying which RAM bank has the last data at the ith address in the RAM banks and defining k status words for valid data among the (k+1) RAM banks. Write data is written to the write address of a valid RAM bank for a write operation in the absence of RAM bank read address contention. Write data is written to the write address of a different RAM bank that has no valid data for a write operation if there is contention with the RAM bank read address RADDR of a read operation. The status register is updated to identify the RAM bank of the write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.