Patent · US Active

Dual port SRAM with dummy read recovery

US9129707B2 · kind B2 · utility

20Cited by

3References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Kao-Cheng Lin · Taipei, TW
Wei Min Chan · Sunnyvale, US
Yen-Huei Chen · Hengshan, TW

Key dates

Filing date	Oct 2, 2013
Grant date	Sep 8, 2015
Priority date	—
Expiry date	Nov 22, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated includes a dual port memory cell such as a SRAM cell. A first port dummy read recovery block couples the first port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the second port bit line, and couples the first port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the second port complementary bit line. A second port dummy read recovery block couples the second port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the first port bit line, and couples the second port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the first port complementary bit line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.