Silicon recess ETCH and epitaxial deposit for shallow trench isolation (STI)
US9129823B2 · kind B2 · utility
3Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2013 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Apr 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.