Enhanced FinFET process overlay mark
US9129974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2014 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Aug 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.