Vertical MOSFET transistor with a vertical capacitor region
US9129991B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 9, 2014 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Apr 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to manufacture a vertical capacitor region that comprises a plurality of trenches, wherein the portions of the semiconductor region in between the trenches comprise an impurity. This allows for the trenches to be placed in closer vicinity to each other, thus improving the capacitance per unit area ratio. The total capacitance of the device is defined by two series components, that is, the capacitance across the dielectric liner, and the depletion capacitance of the silicon next to the trench. An increase of the voltage on the capacitor increases the depletion in the silicon and the depletion capacitance as a result, such that the overall capacitance is reduced. This effect may be countered by minimizing the depletion region which may be achieved by ensuring that the silicon adjacent to the capacitor is as highly doped as possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.