Semiconductor memory devices and methods of fabricating the same
US9130054B2 · kind B2 · utility
25Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Sep 8, 2015 |
| Priority date | — |
| Expiry date | Dec 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.