System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits

US9130116B1 · kind B1 · utility

Assignee

• Hypres, Inc. · US

Inventors

• Sergey K. Tolpygo · Putnam Valley, US
• Denis Amparo · White Plains, US
• Richard Hunt · Park Ridge, US
• John Vivalda · Poughkeepsie, US
• Daniel Yohannes · Stamford, US

Key dates

• Filing date: May 6, 2013
• Grant date: Sep 8, 2015
• Expiry date: Sep 12, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes. These preferred and other methods may be applied to digital circuits based on Rapid Single Flux Quantum logic, and to quantum computing using Josephson junction qubits.