Patent · US Active

Multiplexer flop

US9130549B2 · kind B2 · utility

4Cited by

7References

19Claims

0Family size

Assignee

Cavium, LLC. · US

Inventors

Suresh Balasubramanian · Cupertino, US
Nitin Mohan · San Francisco, US
Manan Salvi · Newton, US

Key dates

Filing date	Mar 18, 2014
Grant date	Sep 8, 2015
Priority date	—
Expiry date	Mar 18, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/0372
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.