Method and apparatus for device testing using multiple processing paths
US9134377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Oct 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31917
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
According to some aspects, a method of operating an automatic test system comprising a plurality of paths and programmed with a test pattern is provided. One such method comprises executing vectors in the test pattern with circuitry comprising a plurality of paths, the executing comprising upon processing, in a first of the plurality of paths, the operation portion of a vector specifying an operation capable of generating a branch in the flow of execution of the vectors in the test pattern to a non-sequential location in the test pattern, initiating processing of the test pattern in a second of the plurality of paths from the non-sequential location. Some aspects include a system for executing instructions comprising a plurality of paths comprising control circuitry to initiate processing of operation portions from sequential locations of a memory within an available path of the plurality of paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.