Patent · US Active

Methods for construction and optimization of a clock tree plan for reduced power consumption

US9135375B1 · kind B1 · utility

33Cited by

22References

21Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Ankush Sood · San Jose, US
Aaron Paul Hurst · Berkeley, US

Key dates

Filing date	Mar 15, 2013
Grant date	Sep 15, 2015
Priority date	—
Expiry date	Mar 15, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment of the invention, a method of physical clock topology planning for designing integrated circuits is disclosed. The method includes reading an initial placed netlist of an integrated circuit design and a floorplan of the integrated circuit design, analyzing the integrated circuit design to determine potential enable signals to gate clock signals that clock the plurality of flip flops to reduce power consumption; simultaneously optimizing and placing the clock enable logic gates to gate clock signals to the plurality of flip flops; and minimizing timing variation of the clock signals to the plurality of flip flops.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.