Systems, methods, and media for assertion-based verification of devices
US9135382B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2012 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Apr 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for functionally verifying the performance of a system on a chip (SOC) are provided herein. According to some embodiments, the methods may include at least the steps of analyzing a verification log, via a functional verification system, to determine signatures by correlating a pattern of at least one of triggered and untriggered assertions in one or more blocks of a plurality of blocks to behaviors of at least one of the SOC and the one or more blocks of the plurality of blocks. Exemplary methods also include categorizing signatures according to the behaviors, and storing similar signatures based upon the categorization in a database.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.