Boosted read write word line
US9135971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2013 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jul 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.