Method for integrated circuit patterning
US9136106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Dec 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.