3D semiconductor device and structure with back-bias
US9136153B2 · kind B2 · utility
36Cited by
339References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 8, 2012 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jun 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.