Stacked semiconductor package
US9136249B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2012 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Sep 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor package includes a first semiconductor chip having one surface, and an other surface which faces away from the one surface, and first through electrodes which pass through the one surface and the other surface and project out of the other surface; a second semiconductor chip stacked over the one surface of the first semiconductor chip and having second through electrodes which are connected with the first through electrodes; a heat dissipation member disposed over the second semiconductor chip; and a first heat absorbing member disposed to face the other surface of the first semiconductor chip and defined with through holes into which projecting portions of the first through electrodes are inserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.