Inverter logic devices including graphene field effect transistor having tunable barrier
US9136336B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2012 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Aug 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.