Doped protection layer for contact formation
US9136340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2013 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jun 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having a first doped region and a second doped region, and a gate stack formed on the semiconductor substrate. The semiconductor device also includes a main spacer layer formed on a sidewall of the gate stack. The semiconductor device further includes a protection layer formed between the main spacer layer and the semiconductor substrate, and the protection layer is doped with a quadrivalent element. In addition, the semiconductor device includes an insulating layer formed on the semiconductor substrate and the gate stack, and a contact formed in the insulating layer. The contact has a first portion contacting the first doped region and has a second portion contacting the second doped region. The first region extends deeper into the semiconductor substrate than the second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.