Reduced uncorrectable memory errors
US9136873B2 · kind B2 · utility
6Cited by
0References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2013 |
| Grant date | Sep 15, 2015 |
| Priority date | — |
| Expiry date | Jul 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.