Method for lithography patterning
US9140987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2014 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Feb 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing resist outgassing for EUV lithography is disclosed. The method includes forming a material layer over a substrate wherein a top surface of the material layer contains a certain concentration of a quencher or a base. The method further includes forming a resist layer over the top surface of the material layer and exposing the resist layer to a EUV radiation for patterning. The quencher or the base underneath the resist layer acts to suppress resist outgassing during the EUV exposure. The material layer itself may serve as a hard mask layer or an anti-reflection layer for the patterning process, in addition to being the carrier of the quencher or the base. The method can be used in other types of lithography, such as e-beam lithography, for reducing resist outgassing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.