Device and method for selective reduced power mode in volatile memory units
US9141178B2 · kind B2 · utility
1Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2010 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Feb 27, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing device comprises a first memory, a second memory, data transfer circuitry, power gating circuitry, and a controller. The first memory comprises at least two volatile memory units. The controller receives or generates a request for setting the information processing device into a reduced power mode; in response to the request, it selects specific memory units among the memory units; controls the data transfer circuitry to transfer data from the selected memory units to the second memory; and controls the power gating circuitry to power down the selected memory units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.