Patent · US Active

Processor having per core and package level P0 determination functionality

US9141426B2 · kind B2 · utility

4Cited by

4References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Malini K. Bhandaru · San Jose, US
Matthew Bace · Arlington, US
A Leonard Brown · Weston, US
Ian M. Steiner · Hillsboro, US
Vivek Garg · San Mateo, US
Eric J. Dehaemer · Shrewsbury, US
Scott P. Bobholz · Bolton, US

Key dates

Filing date	Sep 28, 2012
Grant date	Sep 22, 2015
Priority date	—
Expiry date	Feb 15, 2033

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.