Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data
US9141740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2011 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Feb 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are methods, systems, and articles of manufacture for implementing full-chip optimization across block boundaries with reduced physical design data. Some embodiments create a partial netlist and reduced physical data by identifying and including side instance(s) or side path(s) in the reduced physical data and then include or exclude side instance(s) or side path(s) in the reduced physical data. The method or the system may then perform full-chip optimization across individual block boundaries with the reduced physical data. Some embodiments further merge the post-optimization data back into the original data while reducing logic and physical disturbance to existing designs. Some embodiments anchor driver instance(s) that correspond to excluded side instance(s) or side path(s) to ensure LEC cleanliness and may further trim timing graph(s) based at least on the partial netlist. Some embodiments account for parasitics without static parasitic files. Various embodiments apply to both hierarchical and non-hierarchical designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.