Dongzi Liu
5Patents
3h-index
9Co-inventors
42Inventor score
Filing activity: Dec 26, 2007 → Feb 2, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9026978B1 | Reverse interface logic model for optimizing physical hierarchy under full chip constraint | Physics | 27 | Active |
| US9141740B2 | Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data | Physics | 9 | Active |
| US9639644B1 | Method and apparatus for master-clone optimization during circuit analysis | Physics | 4 | Active |
| US7930675B2 | Method and system for implementing timing analysis and optimization of an electronic design based upon extended regions of analysis | Physics | 3 | Active |
| US9652582B1 | Multi-instantiated block timing optimization | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.