Dual asynchronous and synchronous memory system

US9142272B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gary A. Van Huben · Poughkeepsie, US
• Patrick J. Meaney · Poughkeepsie, US
• John S. Dodson · Pflugerville, US
• Scot H. Rider · Pleasant Valley, US
• James C. Gregerson · Hyde Park, US
• Eric E. Retter · Austin, US
• Irving G. Baysah · Hutto, US
• Glenn D. Gilda · Binghamton, US
• Lawrence D. Curley · Endwell, US
• Vesselina K. Papazova · Highland, US

Key dates

• Filing date: Mar 15, 2013
• Grant date: Sep 22, 2015
• Expiry date: Sep 8, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/4076
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.