John S. Dodson
24Patents
5h-index
22Co-inventors
69Inventor score
Filing activity: Jul 30, 1999 → Aug 30, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6470442B1 | Processor assigning data to hardware partition based on selectable hash of data address | Physics | 30 | Expired |
| US9142272B2 | Dual asynchronous and synchronous memory system | Physics | 8 | Active |
| US6823471B1 | Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem | Physics | 6 | Expired |
| US6658556B1 | Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction | Physics | 6 | Expired |
| US9318171B2 | Dual asynchronous and synchronous memory system | Physics | 6 | Active |
| US6516404B1 | Data processing system having hashed architected processor facilities | Physics | 5 | Expired |
| US6249911A | Optimizing compiler for generating store instructions having memory hierarchy control bits | Physics | 4 | Expired |
| US9136987B2 | Replay suspension in a memory system | Physics | 4 | Active |
| US6249843A | Store instruction having horizontal memory hierarchy control bits | Physics | 3 | Expired |
| US6446165B1 | Address dependent caching behavior within a data processing system having HSA (hashed storage architecture) | Physics | 3 | Expired |
| US10297335B2 | Tracking address ranges for computer memory errors | Physics | 3 | Active |
| US10353669B2 | Managing entries in a mark table of computer memory errors | Physics | 2 | Active |
| US10338999B2 | Confirming memory marks indicating an error in computer memory | Physics | 2 | Active |
| US10304560B2 | Performing error correction in computer memory | Physics | 2 | Active |
| US6598118B1 | Data processing system with HSA (hashed storage architecture) | Physics | 1 | Expired |
| US6449691B1 | Asymmetrical cache properties within a hashed storage subsystem | Physics | 1 | Expired |
| US6253286A | Apparatus for adjusting a store instruction having memory hierarchy control bits | Physics | 1 | Expired |
| US11017875B2 | Tracking address ranges for computer memory errors | Physics | 0 | Active |
| US10649511B2 | Scalable data collection for system management | Emerging Cross-Sectional Technologies | 0 | Active |
| US6230242A | Store instruction having vertical memory hierarchy control bits | Physics | 0 | Expired |
| US12118236B2 | Dynamically allocating memory controller resources for extended prefetching | Physics | 0 | Active |
| US10971246B2 | Performing error correction in computer memory | Physics | 0 | Active |
| US10317964B2 | Scalable data collection for system management | Emerging Cross-Sectional Technologies | 0 | Active |
| US9250666B2 | Scalable data collection for system management | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.