Efficient smart verify method for programming 3D non-volatile memory
US9142302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2014 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | May 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.