Semiconductor package having etched foil capacitor integrated into leadframe
US9142496B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2014 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Jul 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed. Sidewalls of the first metal are coplanar with the foil sidewalls. The second mask is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.