Semiconductor devices having stacked solder bumps with intervening metal layers to provide electrical interconnections
US9142498B2 · kind B2 · utility
5Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2013 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Jun 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical interconnection can be provided using a bump stack including at least two solder bumps which are stacked on one another and at least one intermediate layer interposed between the at least stacked two solder bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.