Field plate assisted resistance reduction in a semiconductor device
US9142625B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2012 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Mar 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/112
Abstract
Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.