Delay compensation circuit
US9143115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2015 |
| Grant date | Sep 22, 2015 |
| Priority date | — |
| Expiry date | Mar 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/04123
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a delay compensation circuit (221, 222) that further includes a terminal for receiving a varying signal from a circuit external to the integrated circuit; a sampler circuit that samples and holds a present value of the varying signal at each occurrence of a transition in a digital signal; an integrator, coupled to the sampler circuit, that integrates a voltage difference between a sample of the varying signal and a reference signal, and that outputs results of the integration, wherein a time constant of the integrator is greater than a period of the varying signal; a waveform generator that generates a decreasing voltage in response to a transition in a second digital signal; and a comparator that has one input terminal for receiving the decreasing voltage, an inverted input terminal for receiving the results, and an output terminal for outputting a signal that generates an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.