Coalescing memory transactions
US9146774B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Mar 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0613
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transactional memory system coalesces two outermost transactions in a transactional memory environment. A processor of the transactional memory system executes a first transaction begin instruction of a first outermost transaction and processes the first transaction. Based on encountering a first transaction end instruction of the first outermost transaction, the processor determines whether the first transaction is to-be coalesced with a second outermost transaction. Based on a determination that the first outermost transaction is to-be coalesced, the processor does not commit store data of the first outermost transaction to memory prior to processing the second outermost transaction. Based on encountering a second transaction begin instruction of the second outermost transaction, the processor processes the second transaction. Based on encountering a second transaction end instruction of the second outermost transaction, the processor commits the store data of the coalesced first outermost transaction and second outermost transaction to memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.