Management of bit line errors based on a stored set of data
US9146824B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2012 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Jul 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes systems and techniques relating to management of bit line errors based on a stored set of data. In some implementations, a system can include a device including non-volatile solid state memory and a memory controller. The memory controller can be configured to identify, from the solid state memory of the device, one or more bit line errors for the device upon power up of the system, construct a set of data corresponding to the one or more bit line errors for the device, store the set of data, at least in part, in the device, and, upon a subsequent power up of the system, identify the one or more bit line errors for the device from the stored set of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.