Analysis of chip-mean variation and independent intra-die variation for chip yield determination
US9147031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Jan 31, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for determining a chip yield are disclosed. One system includes a first level integration solver and a second level integration solver. The first level integration solver is configured to obtain a first probability distribution function modeling variations within a chip and to perform a discontinuous first level integration with the first probability distribution function. In addition, the second level integration solver is implemented by a hardware processor and is configured to perform a continuous second level integration based on a second probability distribution function modeling variations between dies to determine the chip yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.