Memory device and method of controlling leakage current within such a memory device
US9147451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Dec 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column group includes circuitry to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell has coupling circuitry connected between the associated read bit line and a second voltage level different to the first voltage level. During read operation the coupling circuitry associated with the activated memory cell selectively discharges the associated read bit line towards the second voltage level dependent on the data value stored within that activated memory cell. The clamping circuitry connects the associated read bit line to the second voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.