Patent · US Active

System architecture with multiple memory types, including programmable impedance memory elements

US9147464B1 · kind B1 · utility

3Cited by

12References

21Claims

0Family size

Assignee

Adesto Technologies Corporation · US

Inventors

Ed McKernan · West Lake Hills, US
Malcolm Wing · Menlo Park, US
Ravi Sunkavalli · Santa Clara, US

Key dates

Filing date	Mar 18, 2013
Grant date	Sep 29, 2015
Priority date	—
Expiry date	Jul 26, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C14/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system can include a first memory section comprising a plurality of volatile memory cells accessible via a first data path having a first bit width; a second memory section comprising a plurality of programmable impedance memory cells, each having at least one solid electrolyte layer; and a second data path configured to transfer data between the first and second memory sections independent of the first data path, the second data path having a greater bit width than the first data path.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.