Retention logic for non-volatile memory
US9147501B2 · kind B2 · utility
5Cited by
9References
15Claims
0Family size
Assignee
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Key dates
| Filing date | May 28, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Oct 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.