Method for fabricating a strained structure
US9147594B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Jul 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor including a substrate which includes, a fin structure, the fin structure having a top surface. The field effect transistor further including an isolation in the substrate and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the fin structure and the isolation structure. The S/D recess cavity includes a lower portion, the lower portion further includes a first strained layer, a first dielectric film and a second dielectric film, wherein the first strained layer is disposed between the first dielectric film and the second dielectric film. The S/D recess cavity further includes an upper portion including a second strained layer overlying the first strained layer, wherein a ratio of a height of the upper portion to a height of the lower portion ranges from about 0.8 to about 1.2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.