Erasable programmable single-ploy nonvolatile memory
US9147690B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2013 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | May 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/687
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in a N-well region; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.