Tunnel transistor structure integrated with a resistance random access memory (RRAM) and a manufacturing method thereof
US9147835B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2012 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Oct 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
The invention relates to the technical field of semiconductor memories, in particular to a tunnel transistor structure integrated with a resistance random access memory and a manufacturing method thereof. The tunnel transistor structure in the present invention comprises a semiconductor substrate, and a tunnel transistor and a resistance random access memory formed on the semiconductor substrate, wherein the gate dielectric layer of the tunnel transistor extends to the surface of a drain region of the tunnel transistor; the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms the resistance-variable storage layer of the resistance random access memory. In this invention, the high-quality gate dielectric layer of the tunnel transistor and the resistance-variable storage layer of the resistance random access memory are obtained by primary atomic layer deposition which integrates the resistance random access memory and tunnel transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.