Auto-phase synchronization in delay locked loops
US9148157B2 · kind B2 · utility
1Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2014 |
| Grant date | Sep 29, 2015 |
| Priority date | — |
| Expiry date | Aug 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Tuning circuitry may include a controller that is configured to determine a phase difference for a pair of signals generated at different points in a master delay line of a master-slave delay locked loop (DLL) circuit. One of signals of the pair may be communicated through a slave delay line of the master-slave DLL circuit before the phase difference is determined. A programming delay value used to set a phase delay of the slave delay line may be adjusted or tuned based on the phase difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.