Maintaining processor resources during architectural events
US9152561B2 · kind B2 · utility
1Cited by
16References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2014 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Dec 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.