Robert T. George
24Patents
9h-index
29Co-inventors
71Inventor score
Filing activity: Dec 20, 2000 → May 2, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6681292B2 | Distributed read and write caching implementation for optimized input/output applications | Physics | 179 | Expired |
| US7024555B2 | Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment | Physics | 34 | Expired |
| US7552255B1 | Dynamically partitioning pipeline resources | Physics | 33 | Active |
| US7552254B1 | Associating address space identifiers with active contexts | Physics | 33 | Active |
| US7562179B2 | Maintaining processor resources during architectural events | Physics | 24 | Expired |
| US6772298B2 | Method and apparatus for invalidating a cache line without data return in a multi-node architecture | Physics | 15 | Expired |
| US7546422B2 | Method and apparatus for the synchronization of distributed caches | Physics | 10 | Expired |
| US8046539B2 | Method and apparatus for the synchronization of distributed caches | Physics | 9 | Active |
| US7089362B2 | Cache memory eviction policy for combining write transactions | Physics | 9 | Expired |
| US7162546B2 | Reordering unrelated transactions from an ordered interface | Physics | 5 | Expired |
| US8788790B2 | Maintaining processor resources during architectural events | Physics | 2 | Active |
| US7904694B2 | Maintaining processor resources during architectural events | Physics | 1 | Active |
| US9152561B2 | Maintaining processor resources during architectural events | Physics | 1 | Active |
| US10740249B2 | Maintaining processor resources during architectural events | Physics | 1 | Active |
| US10303620B2 | Maintaining processor resources during architectural events | Physics | 1 | Active |
| US7921293B2 | Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment | Physics | 1 | Active |
| US9507730B2 | Maintaining processor resources during architectural events | Physics | 1 | Active |
| US9164901B2 | Maintaining processor resources during architectural events | Physics | 0 | Active |
| US7899972B2 | Maintaining processor resources during architectural events | Physics | 0 | Active |
| US9996475B2 | Maintaining processor resources during architectural events | Physics | 0 | Active |
| US9086958B2 | Maintaining processor resources during architectural events | Physics | 0 | Active |
| US8543793B2 | Maintaining processor resources during architectural events | Physics | 0 | Active |
| US8806172B2 | Maintaining processor resources during architectural evens | Physics | 0 | Active |
| US9164918B2 | Maintaining processor resources during architectural events | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.