Providing bus resiliency in a hybrid memory system
US9152584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2013 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Apr 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.